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Items: 1 to 20 of 98

1.

Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing.

Fuller EJ, Keene ST, Melianas A, Wang Z, Agarwal S, Li Y, Tuchman Y, James CD, Marinella MJ, Yang JJ, Salleo A, Talin AA.

Science. 2019 May 10;364(6440):570-574. doi: 10.1126/science.aaw5581. Epub 2019 Apr 25.

PMID:
31023890
2.

Low-Voltage, CMOS-Free Synaptic Memory Based on LiXTiO2 Redox Transistors.

Li Y, Fuller EJ, Asapu S, Agarwal S, Kurita T, Yang JJ, Talin AA.

ACS Appl Mater Interfaces. 2019 Oct 10. doi: 10.1021/acsami.9b14338. [Epub ahead of print]

PMID:
31559816
3.

A Floating Gate Memory with U-Shape Recessed Channel for Neuromorphic Computing and MCU Applications.

Gan LR, Wang YR, Chen L, Zhu H, Sun QQ.

Micromachines (Basel). 2019 Aug 23;10(9). pii: E558. doi: 10.3390/mi10090558.

4.

Nanoionics-Based Three-Terminal Synaptic Device Using Zinc Oxide.

Balakrishna Pillai P, De Souza MM.

ACS Appl Mater Interfaces. 2017 Jan 18;9(2):1609-1618. doi: 10.1021/acsami.6b13746. Epub 2017 Jan 5.

5.

Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide.

Sangwan VK, Lee HS, Bergeron H, Balla I, Beck ME, Chen KS, Hersam MC.

Nature. 2018 Feb 21;554(7693):500-504. doi: 10.1038/nature25747.

PMID:
29469093
6.

Fully parallel write/read in resistive synaptic array for accelerating on-chip learning.

Gao L, Wang IT, Chen PY, Vrudhula S, Seo JS, Cao Y, Hou TH, Yu S.

Nanotechnology. 2015 Nov 13;26(45):455204.

PMID:
26491032
7.

Self-selective van der Waals heterostructures for large scale memory array.

Sun L, Zhang Y, Han G, Hwang G, Jiang J, Joo B, Watanabe K, Taniguchi T, Kim YM, Yu WJ, Kong BS, Zhao R, Yang H.

Nat Commun. 2019 Jul 18;10(1):3161. doi: 10.1038/s41467-019-11187-9.

8.

Organic one-transistor-type nonvolatile memory gated with thin ionic liquid-polymer film for low voltage operation.

Hwang SK, Park TJ, Kim KL, Cho SM, Jeong BJ, Park C.

ACS Appl Mater Interfaces. 2014 Nov 26;6(22):20179-87. doi: 10.1021/am505750v. Epub 2014 Nov 6.

PMID:
25341965
9.

One-Transistor-One-Transistor (1T1T) Optoelectronic Nonvolatile MoS2 Memory Cell with Nondestructive Read-Out.

Lee D, Kim S, Kim Y, Cho JH.

ACS Appl Mater Interfaces. 2017 Aug 9;9(31):26357-26362. doi: 10.1021/acsami.7b07077. Epub 2017 Jul 26.

PMID:
28707472
10.

Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications.

Merced-Grafals EJ, Dávila N, Ge N, Williams RS, Strachan JP.

Nanotechnology. 2016 Sep 9;27(36):365202. doi: 10.1088/0957-4484/27/36/365202. Epub 2016 Aug 1.

PMID:
27479054
11.

Optoelectronic Properties of Printed Photogating Carbon Nanotube Thin Film Transistors and Their Application for Light-Stimulated Neuromorphic Devices.

Shao L, Wang H, Yang Y, He Y, Tang Y, Fang H, Zhao J, Xiao H, Liang K, Wei M, Xu W, Luo M, Wan Q, Hu W, Gao T, Cui Z.

ACS Appl Mater Interfaces. 2019 Mar 27;11(12):12161-12169. doi: 10.1021/acsami.9b02086. Epub 2019 Mar 14.

PMID:
30817113
12.

Single- and double-gate synaptic transistor with TaO x gate insulator and IGZO channel layer.

Beom K, Yang P, Park D, Kim HJ, Lee HH, Kang CJ, Yoon TS.

Nanotechnology. 2019 Jan 11;30(2):025203. doi: 10.1088/1361-6528/aae8d2. Epub 2018 Nov 2.

PMID:
30387440
13.

A 2-transistor/1-resistor artificial synapse capable of communication and stochastic learning in neuromorphic systems.

Wang Z, Ambrogio S, Balatti S, Ielmini D.

Front Neurosci. 2015 Jan 15;8:438. doi: 10.3389/fnins.2014.00438. eCollection 2014.

14.

Binarized Neural Network with Silicon Nanosheet Synaptic Transistors for Supervised Pattern Classification.

Kim S, Choi B, Yoon J, Lee Y, Kim HD, Kang MH, Choi SJ.

Sci Rep. 2019 Aug 12;9(1):11705. doi: 10.1038/s41598-019-48048-w.

15.

Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit.

Brink S, Nease S, Hasler P.

Neural Netw. 2013 Sep;45:39-49. doi: 10.1016/j.neunet.2013.02.011. Epub 2013 Mar 7.

PMID:
23541925
16.

Energy Scaling Advantages of Resistive Memory Crossbar Based Computation and Its Application to Sparse Coding.

Agarwal S, Quach TT, Parekh O, Hsia AH, DeBenedictis EP, James CD, Marinella MJ, Aimone JB.

Front Neurosci. 2016 Jan 6;9:484. doi: 10.3389/fnins.2015.00484. eCollection 2015.

17.

Nonvolatile Transistor Memory with Self-Assembled Semiconducting Polymer Nanodomain Floating Gates.

Wang W, Kim KL, Cho SM, Lee JH, Park C.

ACS Appl Mater Interfaces. 2016 Dec 14;8(49):33863-33873. Epub 2016 Dec 2.

PMID:
27960399
18.

Graphene nano-floating gate transistor memory on plastic.

Jang S, Hwang E, Cho JH.

Nanoscale. 2014 Dec 21;6(24):15286-92. doi: 10.1039/c4nr04117h. Epub 2014 Nov 10.

PMID:
25382657
19.

A correlated nickelate synaptic transistor.

Shi J, Ha SD, Zhou Y, Schoofs F, Ramanathan S.

Nat Commun. 2013;4:2676. doi: 10.1038/ncomms3676.

PMID:
24177330
20.

Extremely Low Operating Current Resistive Memory Based on Exfoliated 2D Perovskite Single Crystals for Neuromorphic Computing.

Tian H, Zhao L, Wang X, Yeh YW, Yao N, Rand BP, Ren TL.

ACS Nano. 2017 Dec 26;11(12):12247-12256. doi: 10.1021/acsnano.7b05726. Epub 2017 Dec 11.

PMID:
29200259

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