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Items: 1 to 20 of 108

1.

Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor.

Cheng YC, Chen HB, Han MH, Lu NH, Su JJ, Shao CS, Wu YC.

Nanoscale Res Lett. 2014 Aug 13;9(1):392. doi: 10.1186/1556-276X-9-392. eCollection 2014.

2.

Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor.

Chen L, Cai F, Otuonye U, Lu WD.

Nano Lett. 2016 Jan 13;16(1):420-6. doi: 10.1021/acs.nanolett.5b04038. Epub 2015 Dec 21.

PMID:
26674542
3.

Ultra Thin Poly-Si Nanosheet Junctionless Field-Effect Transistor with Nickel Silicide Contact.

Lin YR, Tsai WT, Wu YC, Lin YH.

Materials (Basel). 2017 Nov 7;10(11). pii: E1276. doi: 10.3390/ma10111276.

4.

Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure.

Cheng YC, Chen HB, Su JJ, Shao CS, Wang CP, Chang CY, Wu YC.

Nanoscale Res Lett. 2014 Dec;9(1):2494. doi: 10.1186/1556-276X-9-669. Epub 2014 Dec 11.

5.

Self-aligned top-gate amorphous indium zinc oxide thin-film transistors exceeding low-temperature poly-Si transistor performance.

Park JC, Lee HN, Im S.

ACS Appl Mater Interfaces. 2013 Aug 14;5(15):6990-5. doi: 10.1021/am401128p. Epub 2013 Jul 17.

PMID:
23823486
6.

Low-voltage operation of ZrO2-gated n-type thin-film transistors based on a channel formed by hybrid phases of SnO and SnO2.

Chu HC, Shen YS, Hsieh CH, Huang JH, Wu YH.

ACS Appl Mater Interfaces. 2015 Jul 22;7(28):15129-37. doi: 10.1021/acsami.5b02941. Epub 2015 Jul 13.

PMID:
26148216
7.

A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory.

Yeh MS, Wu YC, Liu KC, Chung MH, Jhan YR, Hung MF, Chen LC.

Nanoscale Res Lett. 2014 Nov 6;9(1):603. doi: 10.1186/1556-276X-9-603. eCollection 2014.

8.

A Vertically Integrated Junctionless Nanowire Transistor.

Lee BH, Hur J, Kang MH, Bang T, Ahn DC, Lee D, Kim KH, Choi YK.

Nano Lett. 2016 Mar 9;16(3):1840-7. doi: 10.1021/acs.nanolett.5b04926. Epub 2016 Feb 29.

PMID:
26885948
9.

The effects of nanometal-induced crystallization on the electrical characteristics of bottom-gate poly-Si thin-film transistors.

Lee IC, Yang PY, Hu MJ, Wang JL, Tsai CC, Chang CT, Cheng HC.

J Nanosci Nanotechnol. 2011 Jul;11(7):5612-7.

PMID:
22121579
10.

Modulating Thin Film Transistor Characteristics by Texturing the Gate Metal.

Nair A, Bhattacharya P, Sambandan S.

Sci Rep. 2017 Dec 20;7(1):17932. doi: 10.1038/s41598-017-18111-5.

11.

Transforming gate misalignment into a unique opportunity to facilitate steep switching in junctionless nanotransistors.

Gupta M, Kranti A.

Nanotechnology. 2016 Nov 11;27(45):455204. Epub 2016 Oct 7.

PMID:
27713187
12.

High performance thin film transistor with ZnO channel layer deposited by DC magnetron sputtering.

Moon YK, Moon DY, Lee SH, Jeong CO, Park JW.

J Nanosci Nanotechnol. 2008 Sep;8(9):4557-60.

PMID:
19049057
13.

All two-dimensional, flexible, transparent, and thinnest thin film transistor.

Das S, Gulotty R, Sumant AV, Roelofs A.

Nano Lett. 2014 May 14;14(5):2861-6. doi: 10.1021/nl5009037. Epub 2014 Apr 22. Erratum in: Nano Lett. 2016 Feb 10;16(2):1515.

PMID:
24754722
14.

Fully transparent flexible tin-doped zinc oxide thin film transistors fabricated on plastic substrate.

Han D, Zhang Y, Cong Y, Yu W, Zhang X, Wang Y.

Sci Rep. 2016 Dec 12;6:38984. doi: 10.1038/srep38984.

15.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

Jaehnike F, Pham DV, Anselmann R, Bock C, Kunze U.

ACS Appl Mater Interfaces. 2015 Jul 1;7(25):14011-7. doi: 10.1021/acsami.5b03105. Epub 2015 Jun 18.

PMID:
26039187
16.

High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits.

Wu TT, Huang WH, Yang CC, Chen HC, Hsieh TY, Lin WS, Kao MH, Chen CH, Yao JY, Jian YL, Hsu CC, Lin KL, Shen CH, Chueh YL, Shieh JM.

Sci Rep. 2017 May 2;7(1):1368. doi: 10.1038/s41598-017-01012-y.

17.

Performance enhancement of carbon nanotube thin film transistor by yttrium oxide capping.

Xia J, Zhao J, Meng H, Huang Q, Dong G, Zhang H, Liu F, Mao D, Liang X, Peng L.

Nanoscale. 2018 Mar 1;10(9):4202-4208. doi: 10.1039/c7nr08676h.

PMID:
29450427
18.

Low-Temperature Growth of Indium Oxide Thin Film by Plasma-Enhanced Atomic Layer Deposition Using Liquid Dimethyl(N-ethoxy-2,2-dimethylpropanamido)indium for High-Mobility Thin Film Transistor Application.

Kim HY, Jung EA, Mun G, Agbenyeke RE, Park BK, Park JS, Son SU, Jeon DJ, Park SK, Chung TM, Han JH.

ACS Appl Mater Interfaces. 2016 Oct 12;8(40):26924-26931. Epub 2016 Sep 27.

PMID:
27673338
19.

Enhanced sensitivity of double gate junctionless transistor architecture for biosensing applications.

Parihar MS, Kranti A.

Nanotechnology. 2015 Apr 10;26(14):145201. doi: 10.1088/0957-4484/26/14/145201. Epub 2015 Mar 16.

PMID:
25771821
20.

Lamination method for the study of interfaces in polymeric thin film transistors.

Chabinyc ML, Salleo A, Wu Y, Liu P, Ong BS, Heeney M, McCulloch I.

J Am Chem Soc. 2004 Nov 3;126(43):13928-9.

PMID:
15506746

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