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Items: 1 to 20 of 96

1.

A hot hole-programmed and low-temperature-formed SONOS flash memory.

Chang YM, Yang WL, Liu SH, Hsiao YP, Wu JY, Wu CC.

Nanoscale Res Lett. 2013 Jul 31;8(1):340. doi: 10.1186/1556-276X-8-340.

2.

ZnO/NiO diode-based charge-trapping layer for flash memory featuring low-voltage operation.

Sun CE, Chen CY, Chu KL, Shen YS, Lin CC, Wu YH.

ACS Appl Mater Interfaces. 2015 Apr 1;7(12):6383-90. doi: 10.1021/am507535c. Epub 2015 Mar 17. Erratum in: ACS Appl Mater Interfaces. 2015 May 13;7(18):10067.

PMID:
25781005
3.

Flash Memory Featuring Low-Voltage Operation by Crystalline ZrTiO4 Charge-Trapping Layer.

Shen YS, Chen KY, Chen PC, Chen TC, Wu YH.

Sci Rep. 2017 Mar 8;7:43659. doi: 10.1038/srep43659.

4.

Electronic Structure and Charge-Trapping Characteristics of the Al2O3-TiAlO-SiO2 Gate Stack for Nonvolatile Memory Applications.

Xu W, Zhang Y, Tang Z, Shao Z, Zhou G, Qin M, Zeng M, Wu S, Zhang Z, Gao J, Lu X, Liu J.

Nanoscale Res Lett. 2017 Dec;12(1):270. doi: 10.1186/s11671-017-2040-x. Epub 2017 Apr 13.

5.

Nanographene charge trapping memory with a large memory window.

Meng J, Yang R, Zhao J, He C, Wang G, Shi D, Zhang G.

Nanotechnology. 2015 Nov 13;26(45):455704. doi: 10.1088/0957-4484/26/45/455704. Epub 2015 Oct 22.

PMID:
26489448
6.

Transparent Flash Memory Using Single Ta2O5 Layer for Both Charge-Trapping and Tunneling Dielectrics.

Hota MK, Alshammari FH, Salama KN, Alshareef HN.

ACS Appl Mater Interfaces. 2017 Jul 5;9(26):21856-21863. doi: 10.1021/acsami.7b03078. Epub 2017 Jun 22.

PMID:
28593752
7.

Fabrication and characterization of twin poly-Si thin film transistors EEPROM with a nitride charge trapping layer.

Hung MF, Wu YC, Chiang JH, Chen JH, Chen LC.

J Nanosci Nanotechnol. 2011 Dec;11(12):10419-23.

PMID:
22408918
8.

Tunable charge-trap memory based on few-layer MoS2.

Zhang E, Wang W, Zhang C, Jin Y, Zhu G, Sun Q, Zhang DW, Zhou P, Xiu F.

ACS Nano. 2015 Jan 27;9(1):612-9. doi: 10.1021/nn5059419. Epub 2014 Dec 17.

PMID:
25496773
9.

Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

Wang W, Hwang SK, Kim KL, Lee JH, Cho SM, Park C.

ACS Appl Mater Interfaces. 2015 May 27;7(20):10957-65. doi: 10.1021/acsami.5b02213. Epub 2015 May 15.

PMID:
25943406
10.

Hierarchically built gold nanoparticle supercluster arrays as charge storage centers for enhancing the performance of flash memory devices.

Suresh V, Kusuma DY, Lee PS, Yap FL, Srinivasan MP, Krishnamoorthy S.

ACS Appl Mater Interfaces. 2015 Jan 14;7(1):279-86. doi: 10.1021/am506174s. Epub 2015 Jan 5.

PMID:
25427075
11.

Comparative analysis of trap-based program/erase behaviors with different tunnel barriers.

Li DH, Kim Y, Kim DH, Lee GS, Park BG.

J Nanosci Nanotechnol. 2011 Dec;11(12):10535-8.

PMID:
22408942
12.

Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array.

Cho I, Kim BJ, Ryu SW, Cho JH, Cho J.

Nanotechnology. 2014 Dec 19;25(50):505604. doi: 10.1088/0957-4484/25/50/505604. Epub 2014 Nov 26.

PMID:
25426661
13.
14.

Nonvolatile floating gate memory containing AgInSbTe-SiO2 nanocomposite layer and capping the HfO2/SiO2 composite blocking oxide layer.

Chiang KC, Hsieh TE.

Nanotechnology. 2012 Jun 8;23(22):225703. doi: 10.1088/0957-4484/23/22/225703. Epub 2012 May 10.

PMID:
22571872
15.

Graphene-quantum-dot nonvolatile charge-trap flash memories.

Sin Joo S, Kim J, Kang SS, Kim S, Choi SH, Hwang SW.

Nanotechnology. 2014 Jun 27;25(25):255203. doi: 10.1088/0957-4484/25/25/255203. Epub 2014 Jun 4.

PMID:
24896068
16.

Effect of annealing treatments on photoluminescence and charge storage mechanism in silicon-rich SiNx:H films.

Sahu BS, Delachat F, Slaoui A, Carrada M, Ferblantier G, Muller D.

Nanoscale Res Lett. 2011 Feb 28;6(1):178. doi: 10.1186/1556-276X-6-178.

17.

Characteristics of junctionless charge trap flash memory for 3D stacked NAND flash.

Oh J, Na H, Park S, Sohn H.

J Nanosci Nanotechnol. 2013 Sep;13(9):6413-5.

PMID:
24205672
18.

Titanium-tungsten nanocrystals embedded in a SiO(2)/Al(2)O(3) gate dielectric stack for low-voltage operation in non-volatile memory.

Yang S, Wang Q, Zhang M, Long S, Liu J, Liu M.

Nanotechnology. 2010 Jun 18;21(24):245201. doi: 10.1088/0957-4484/21/24/245201. Epub 2010 May 25.

PMID:
20498524
19.

Isolated nanographene crystals for nano-floating gate in charge trapping memory.

Yang R, Zhu C, Meng J, Huo Z, Cheng M, Liu D, Yang W, Shi D, Liu M, Zhang G.

Sci Rep. 2013;3:2126. doi: 10.1038/srep02126.

20.

Atomic-layer-deposition-assisted ZnO nanoparticles for oxide charge-trap memory thin-film transistors.

Seo GH, Yun DJ, Lee WH, Yoon SM.

Nanotechnology. 2017 Feb 17;28(7):075202. doi: 10.1088/1361-6528/aa535d. Epub 2016 Dec 13.

PMID:
27958196

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