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Items: 1 to 20 of 117

1.

A learning-enabled neuron array IC based upon transistor channel models of biological phenomena.

Brink S, Nease S, Hasler P, Ramakrishnan S, Wunderlich R, Basu A, Degnan B.

IEEE Trans Biomed Circuits Syst. 2013 Feb;7(1):71-81. doi: 10.1109/TBCAS.2012.2197858.

PMID:
23853281
2.

A forecast-based STDP rule suitable for neuromorphic implementation.

Davies S, Galluppi F, Rast AD, Furber SB.

Neural Netw. 2012 Aug;32:3-14. doi: 10.1016/j.neunet.2012.02.018. Epub 2012 Feb 14.

PMID:
22386500
3.

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

Cruz-Albrecht JM, Derosier T, Srinivasa N.

Nanotechnology. 2013 Sep 27;24(38):384011. doi: 10.1088/0957-4484/24/38/384011. Epub 2013 Sep 2.

PMID:
23999447
4.

Neuron array with plastic synapses and programmable dendrites.

Ramakrishnan S, Wunderlich R, Hasler J, George S.

IEEE Trans Biomed Circuits Syst. 2013 Oct;7(5):631-42. doi: 10.1109/TBCAS.2013.2282616. Epub 2013 Oct 18.

PMID:
24144669
5.

Spiking neuron computation with the time machine.

Garg V, Shekhar R, Harris JG.

IEEE Trans Biomed Circuits Syst. 2012 Apr;6(2):142-55. doi: 10.1109/TBCAS.2011.2179544.

PMID:
23852979
6.

An event-based neural network architecture with an asynchronous programmable synaptic memory.

Moradi S, Indiveri G.

IEEE Trans Biomed Circuits Syst. 2014 Feb;8(1):98-107. doi: 10.1109/TBCAS.2013.2255873.

PMID:
24681923
7.

Dynamic evolving spiking neural networks for on-line spatio- and spectro-temporal pattern recognition.

Kasabov N, Dhoble K, Nuntalid N, Indiveri G.

Neural Netw. 2013 May;41:188-201. doi: 10.1016/j.neunet.2012.11.014. Epub 2012 Dec 20.

PMID:
23340243
8.

A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity.

Indiveri G, Chicca E, Douglas R.

IEEE Trans Neural Netw. 2006 Jan;17(1):211-21.

PMID:
16526488
9.

Artificial brains. A million spiking-neuron integrated circuit with a scalable communication network and interface.

Merolla PA, Arthur JV, Alvarez-Icaza R, Cassidy AS, Sawada J, Akopyan F, Jackson BL, Imam N, Guo C, Nakamura Y, Brezzo B, Vo I, Esser SK, Appuswamy R, Taba B, Amir A, Flickner MD, Risk WP, Manohar R, Modha DS.

Science. 2014 Aug 8;345(6197):668-73. doi: 10.1126/science.1254642. Epub 2014 Aug 7.

10.

VLSI circuits implementing computational models of neocortical circuits.

Wijekoon JH, Dudek P.

J Neurosci Methods. 2012 Sep 15;210(1):93-109. doi: 10.1016/j.jneumeth.2012.01.019. Epub 2012 Feb 11.

PMID:
22342970
11.

Energy-efficient neuron, synapse and STDP integrated circuits.

Cruz-Albrecht JM, Yung MW, Srinivasa N.

IEEE Trans Biomed Circuits Syst. 2012 Jun;6(3):246-56. doi: 10.1109/TBCAS.2011.2174152.

PMID:
23853146
12.

A hardware efficient cascadable chip set for ANN's with on-chip backpropagation.

Lehmann T.

Int J Neural Syst. 1993 Dec;4(4):351-8.

PMID:
8049798
13.

A spiking neuron circuit based on a carbon nanotube transistor.

Chen CL, Kim K, Truong Q, Shen A, Li Z, Chen Y.

Nanotechnology. 2012 Jul 11;23(27):275202. doi: 10.1088/0957-4484/23/27/275202. Epub 2012 Jun 19.

PMID:
22710137
14.

Building blocks for electronic spiking neural networks.

van Schaik A.

Neural Netw. 2001 Jul-Sep;14(6-7):617-28. Review.

PMID:
11665758
15.

What can a neuron learn with spike-timing-dependent plasticity?

Legenstein R, Naeger C, Maass W.

Neural Comput. 2005 Nov;17(11):2337-82.

PMID:
16156932
16.

Analog-digital simulations of full conductance-based networks of spiking neurons with spike timing dependent plasticity.

Zou Q, Bornat Y, Saïghi S, Tomas J, Renaud S, Destexhe A.

Network. 2006 Sep;17(3):211-33.

PMID:
17162612
17.

A spiking neuron model: applications and learning.

Christodoulou C, Bugmann G, Clarkson TG.

Neural Netw. 2002 Sep;15(7):891-908.

PMID:
14672166
18.

A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses.

Qiao N, Mostafa H, Corradi F, Osswald M, Stefanini F, Sumislawska D, Indiveri G.

Front Neurosci. 2015 Apr 29;9:141. doi: 10.3389/fnins.2015.00141. eCollection 2015.

19.

An analog memory circuit for spiking silicon neurons.

Elias JG, Northmore DP, Westerman W.

Neural Comput. 1997 Feb 15;9(2):419-40.

PMID:
9117908
20.

Neural learning circuits utilizing nano-crystalline silicon transistors and memristors.

Cantley KD, Subramaniam A, Stiegler HJ, Chapman RA, Vogel EM.

IEEE Trans Neural Netw Learn Syst. 2012 Apr;23(4):565-73. doi: 10.1109/TNNLS.2012.2184801.

PMID:
24805040

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