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Items: 1 to 20 of 86

1.

Fabrication of vertically stacked single-crystalline Si nanowires using self-limiting oxidation.

Wang T, Yu B, Liu Y, Guo Q, Sheng K, Deen MJ.

Nanotechnology. 2012 Jan 13;23(1):015307. doi: 10.1088/0957-4484/23/1/015307. Epub 2011 Dec 8.

PMID:
22156013
2.

Ordered arrays of vertically aligned [110] silicon nanowires by suppressing the crystallographically preferred <100> etching directions.

Huang Z, Shimizu T, Senz S, Zhang Z, Zhang X, Lee W, Geyer N, Gösele U.

Nano Lett. 2009 Jul;9(7):2519-25. doi: 10.1021/nl803558n.

PMID:
19480399
3.
4.

Lateral Ge Diffusion During Oxidation of Si/SiGe Fins.

Brewer WM, Xin Y, Hatem C, Diercks D, Truong VQ, Jones KS.

Nano Lett. 2017 Apr 12;17(4):2159-2164. doi: 10.1021/acs.nanolett.6b04407. Epub 2017 Mar 3.

PMID:
28249115
5.

Vertically Integrated Multiple Nanowire Field Effect Transistor.

Lee BH, Kang MH, Ahn DC, Park JY, Bang T, Jeon SB, Hur J, Lee D, Choi YK.

Nano Lett. 2015 Dec 9;15(12):8056-61. doi: 10.1021/acs.nanolett.5b03460. Epub 2015 Nov 11.

PMID:
26544156
6.

Vertically oriented epitaxial germanium nanowires on silicon substrates using thin germanium buffer layers.

Jung JH, Yoon HS, Kim YL, Song MS, Kim Y, Chen ZG, Zou J, Choi DY, Kang JH, Joyce HJ, Gao Q, Hoe Tan H, Jagadish C.

Nanotechnology. 2010 Jul 23;21(29):295602. doi: 10.1088/0957-4484/21/29/295602. Epub 2010 Jun 29.

PMID:
20585174
7.

Silicon nanowire transistors with a channel width of 4 nm fabricated by atomic force microscope nanolithography.

Martinez J, Martínez RV, Garcia R.

Nano Lett. 2008 Nov;8(11):3636-9. doi: 10.1021/nl801599k. Epub 2008 Oct 1.

PMID:
18826289
8.

Controlled fabrication of silicon nanowires via nanosphere lithograph and metal assisted chemical etching.

Sun B, Shi T, Sheng W, Liao G.

J Nanosci Nanotechnol. 2013 Aug;13(8):5708-14.

PMID:
23882822
9.

Sub-20 nm Si/Ge superlattice nanowires by metal-assisted etching.

Geyer N, Huang Z, Fuhrmann B, Grimm S, Reiche M, Nguyen-Duc TK, de Boor J, Leipner HS, Werner P, Gösele U.

Nano Lett. 2009 Sep;9(9):3106-10. doi: 10.1021/nl900751g.

PMID:
19655719
10.

Bulk synthesis of crystalline and crystalline core/amorphous shell silicon nanowires and their application for energy storage.

Chen H, Xu J, Chen PC, Fang X, Qiu J, Fu Y, Zhou C.

ACS Nano. 2011 Oct 25;5(10):8383-90. doi: 10.1021/nn203166w. Epub 2011 Oct 10.

PMID:
21942645
11.

Interference lithographically defined and catalytically etched, large-area silicon nanocones from nanowires.

Dawood MK, Liew TH, Lianto P, Hong MH, Tripathy S, Thong JT, Choi WK.

Nanotechnology. 2010 May 21;21(20):205305. doi: 10.1088/0957-4484/21/20/205305. Epub 2010 Apr 26.

PMID:
20418606
12.

Single-crystal CdSe nanowires prepared via vapor-phase growth assisted with silicon.

Wang ZY, Zhang LD, Ye CH, Fang XS, Xiao ZD, Kong MG.

J Nanosci Nanotechnol. 2005 Dec;5(12):2088-92.

PMID:
16430145
13.

Top-down fabrication of sub-30 nm monocrystalline silicon nanowires using conventional microfabrication.

Chen S, Bomer JG, van der Wiel WG, Carlen ET, van den Berg A.

ACS Nano. 2009 Nov 24;3(11):3485-92. doi: 10.1021/nn901220g.

PMID:
19856905
14.

Single crystalline PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices.

Lin YC, Lu KC, Wu WW, Bai J, Chen LJ, Tu KN, Huang Y.

Nano Lett. 2008 Mar;8(3):913-8. doi: 10.1021/nl073279r. Epub 2008 Feb 12.

PMID:
18266331
15.
16.

Silicon nanowire circuits fabricated by AFM oxidation nanolithography.

Martínez RV, Martínez J, Garcia R.

Nanotechnology. 2010 Jun 18;21(24):245301. doi: 10.1088/0957-4484/21/24/245301. Epub 2010 May 20.

PMID:
20484797
17.

Integrated freestanding single-crystal silicon nanowires: conductivity and surface treatment.

Lee CH, Ritz CS, Huang M, Ziwisky MW, Blise RJ, Lagally MG.

Nanotechnology. 2011 Feb 4;22(5):055704. doi: 10.1088/0957-4484/22/5/055704. Epub 2010 Dec 22.

PMID:
21178224
18.

Cross-section control of stacked nanowires formed by Bosch process and oxidation.

Zuo X, Wang T, Ng RM, He J, Chan M.

J Nanosci Nanotechnol. 2011 Dec;11(12):10503-5.

PMID:
22408935
19.

Fabrication of single crystalline cadmium nanowires by a facile low temperature vapor phase method.

Mohanty P, Park J, Lee G, Kim B.

J Nanosci Nanotechnol. 2006 Nov;6(11):3376-9.

PMID:
17252769
20.

Au/Ag bilayered metal mesh as a si etching catalyst for controlled fabrication of si nanowires.

Kim J, Han H, Kim YH, Choi SH, Kim JC, Lee W.

ACS Nano. 2011 Apr 26;5(4):3222-9. doi: 10.1021/nn2003458. Epub 2011 Mar 16.

PMID:
21388226

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