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Sensors (Basel). 2012;12(8):10067-85. doi: 10.3390/s120810067. Epub 2012 Jul 25.

Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Author information

1
The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

Abstract

Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

KEYWORDS:

CMOS; SNR; image sensor; low power; snapshot; strong inversion; sub-threshold; wide dynamic range

PMID:
23112588
PMCID:
PMC3472816
DOI:
10.3390/s120810067
[Indexed for MEDLINE]
Free PMC Article

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