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J Nanosci Nanotechnol. 2019 Mar 1;19(3):1295-1300. doi: 10.1166/jnn.2019.16239.

Nano-Programmable Logics Based on Double-Layer Anti-Facing Memristors.

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Department of EE, Chungbuk National University, 1 Chungdae-ro Seowon-gu, Cheongju, 28644, S. Korea.
School of EE, University of Western Australia, 35 Stirling Hwy, Crawley WA, 6009, Australia.


The memristor, as theorized by Chua in 1971 (L. Chua, IEEE Trans. Circuit Theory 18, 507 (1971)), is a two-terminal device whose resistance state is based on the history of charge flow brought about as a result of the voltage applied across its terminals. High-density regular fabrics for nanoscale memristors, such as crossbar arrays, are emerging architectures for system-on-chip (SoC) implementation, which provide both simplified structure and improved performance (W. H. Yu, et al., IEEE Trans. VLSI 20, 1012 (2012)). The advantage of using memristors as the switching devices within crossbar arrays is their nanoscale switching capability, which specifically changes their resistance state between high and low. In this paper, we propose a new nano-programmable logic array (PLA) device in the form of an on anti-facing double-layer memristor array. The PLA is composed of an AND plane and an OR plane merged onto the same layer. The AND and OR planes are stacked vertically such that each layer forms a crossbar architecture; thus, a cross section reveals two anti-facing memristors with 5 layers: the bottom metal layer, a memristive layer, the intermediate metal layer, an anti-facing memristive layer, and the top metal layer. The intermediate metal layer provides its output at the AND plane which is the input of the OR plane, and as such, the input and output nodes of the two logic functions are shared. Thus, the proposed architecture reduces the propagation delay of the AND plane by 70% by sharing the OR plane input wires. Additionally, the anti-facing architecture makes it easy to determine appropriate values for the pull-up and pull-down registers of the PLA.


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