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ACS Appl Mater Interfaces. 2018 Aug 8;10(31):26405-26412. doi: 10.1021/acsami.8b07749. Epub 2018 Jul 24.

Visible Light-Erasable Oxide FET-Based Nonvolatile Memory Operated with a Deep Trap Interface.

Kim T1,2, Lim JW1,2, Lee SH1, Na J1, Jeong J1, Jung KH1,2, Kim G1,2, Yun SJ1,2.

Author information

1
ICT Materials Research Group, Materials & Components Basic Research Division , Electronics and Telecommunications Research Institute (ETRI) , 218 Gajeong-ro , Yuseong-gu, Daejeon 305-700 , South Korea.
2
Department of Advanced Device Engineering , University of Science and Technology , 217 Gajeong-ro , Yuseong-gu, Daejeon 305-350 , South Korea.

Abstract

A new concept of a tunneling oxide-free nonvolatile memory device with a deep trap interface floating gate is proposed. This device demonstrates a high on/off current ratio of 107 and a sizable memory window due to deep traps at the interface between the channel and gate dielectric layers. Interestingly, irradiation with 400 nm light can completely restore the program state to the initial one (performing an erasing process), which is attributed to the visible light-sensitive channel layer. Device reproducibility is enhanced by selectively passivating shallow traps at the interface using in situ H2 plasma treatment. The passivated memory device shows highly reproducible memory operation and on-state current during retention bake tests at 85 °C. One of the most significant advantages of this visible light-erasable oxide field-effect transistor-based nonvolatile memory is its simple structure, which is free from deterioration due to the frequent tunneling processes, as compared to conventional nonvolatile memory devices with tunneling oxides.

KEYWORDS:

nonvolatile memory (NVM); oxide semiconductor; plasma treatment; transistor; visible light

PMID:
29998730
DOI:
10.1021/acsami.8b07749

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