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Nat Nanotechnol. 2018 Jan;13(1):24-28. doi: 10.1038/s41565-017-0010-1. Epub 2017 Dec 18.

Steep-slope hysteresis-free negative capacitance MoS2 transistors.

Si M1,2, Su CJ3, Jiang C1,4, Conrad NJ1,2, Zhou H1,2, Maize KD1,2, Qiu G1,2, Wu CT3, Shakouri A1,2, Alam MA1, Ye PD5,6.

Author information

1
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, 47907, USA.
2
Birck Nanotechnology Center, Purdue University, West Lafayette, IN, 47907, USA.
3
National Nano Device Laboratories, Hsinchu, 300, Taiwan.
4
Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing, 100084, China.
5
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, 47907, USA. yep@purdue.edu.
6
Birck Nanotechnology Center, Purdue University, West Lafayette, IN, 47907, USA. yep@purdue.edu.

Abstract

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption 1,2 . Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier 3 . Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel 4-12 . Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

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PMID:
29255287
DOI:
10.1038/s41565-017-0010-1

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