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Nat Nanotechnol. 2015 Nov;10(11):944-8. doi: 10.1038/nnano.2015.197. Epub 2015 Sep 7.

Solution-processed carbon nanotube thin-film complementary static random access memory.

Author information

1
Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208, USA.
2
Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, Minnesota 55455, USA.
3
Department of Chemistry, Northwestern University, Evanston, Illinois 60208, USA.

Abstract

Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

PMID:
26344184
DOI:
10.1038/nnano.2015.197

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