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Nanotechnology. 2007 Nov 21;18(46):465202. doi: 10.1088/0957-4484/18/46/465202. Epub 2007 Oct 12.

Feasibility study of logic circuits with a spin wave bus.

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1
Device Research Laboratory, Electrical Engineering Department, MARCO Focus Center on Functional Engineered Nano Architectonics (FENA), Western Institute of Nanoelectronics (WIN), University of California at Los Angeles, Los Angeles, CA 90095-1594, USA.

Abstract

We present a feasibility study of logic circuits utilizing spin waves for information transmission and processing. As an alternative approach to the transistor-based architecture, logic circuits with a spin wave bus do not use charge as an information carrier. In this work we describe the general concept of logic circuits with a spin wave bus and illustrate its performance by numerical simulations based on available experimental data. Theoretical estimates and results of numerical simulations on signal attenuation, signal phase velocity, and the minimum spin wave energy required per bit in the spin bus are obtained. The transport parameters are compared with ones for conventional electronic transmission lines. The spin wave bus is not intended to substitute traditional metal interconnects since it has higher signal attenuation and lower signal propagation speed. The potential value of a spin wave bus is, however, an interface between electronic circuits and integrated spintronics circuits. The logic circuits with a spin wave bus allow us to provide wireless read-in and read-out.

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