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Nanotechnology. 2009 Oct 14;20(41):415202. doi: 10.1088/0957-4484/20/41/415202. Epub 2009 Sep 16.

The large-scale integration of high-performance silicon nanowire field effect transistors.

Author information

1
Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA 22030, USA. qli6@gmu.edu

Abstract

In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio (>10(7)). The subthreshold swing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale.

PMID:
19755723
DOI:
10.1088/0957-4484/20/41/415202
[Indexed for MEDLINE]
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