With the availability of modern application specific integrated circuit (ASIC) design tools, simulation packages, and low-cost commercial silicon foundry processes, it is becoming increasingly easy for any laboratory, or small company, to develop a custom ASIC. For stimulation, as well as recording, chips that perform specialized functions can be designed, fabricated, and tested within a time period of 2-3 months. In many cases, the desired functionality can only be obtained by using VLSI design methods. Despite this increase in ASIC functionality, as related to neural engineering applications, there exists no common interface protocol for communicating with, and controlling, neural engineering ASICs. This would be analogous to each company that manufactures PC-based systems to have no common method of communication, e.g. USB, GBIB, RS-232, etc. While it might seem elusive, we propose the specification and development of a universal interface protocol for neural engineering ASICs. We have named this interface, NeuroTalk.