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J Am Chem Soc. 2006 Oct 4;128(39):12851-69.

Gate dielectric chemical structure-organic field-effect transistor performance correlations for electron, hole, and ambipolar organic semiconductors.

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Department of Chemistry and the Materials Research Center, Northwestern University 2145 Sheridan Road, Evanston, IL 60208, USA.


This study describes a general approach for probing semiconductor-dielectric interfacial chemistry effects on organic field-effect transistor performance parameters using bilayer gate dielectrics. Organic semiconductors exhibiting p-/n-type or ambipolar majority charge transport are grown on six different bilayer dielectric structures consisting of various spin-coated polymers/HMDS on 300 nm SiO(2)/p(+)-Si, and are characterized by AFM, SEM, and WAXRD, followed by transistor electrical characterization. In the case of air-sensitive (generally high LUMO energy) n-type semiconductors, dielectric surface modifications induce large variations in the corresponding OTFT performance parameters although the film morphologies and microstructures remain similar. In marked contrast, the device performance of air-stable n-type and p-type semiconductors is not significantly affected by the same dielectric surface modifications. Among the bilayer dielectric structures examined, nonpolar polystyrene coatings on SiO(2) having minimal gate leakage and surface roughness significantly enhance the mobilities of overlying air-sensitive n-type semiconductors to as high as approximately 2 cm(2)/(V s) for alpha,omega-diperfluorohexylcarbonylquaterthiophene polystyrene/SiO(2). Electron trapping due to silanol and carbonyl functionalities at the semiconductor-dielectric interface is identified as the principal origin of the mobility sensitivity to the various surface chemistries in the case of n-type semiconductors having high LUMO energies. Thiophene-based n-type semiconductors exhibiting similar film morphologies and microstructures on various bilayer gate dielectrics therefore provide an incisive means to probe TFT performance parameters versus semiconductor-dielectric interface relationships.

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