The performance of nanostructured semiconductors is frequently limited by interface defects that trap electronic carriers. In particular, high aspect ratio geometries dramatically increase the difficulty of using typical solid-state electrical measurements (multifrequency capacitance- and conductance-voltage testing) to quantify interface trap densities (D it). We report on electrochemical impedance spectroscopy (EIS) to characterize the energy distribution of interface traps at metal oxide/semiconductor interfaces. This method takes advantage of liquid electrolytes, which provide conformal electrical contacts. Planar Al2O3/p-Si and Al2O3/p-Si0.55Ge0.45 interfaces are used to benchmark the EIS data against results obtained from standard electrical testing methods. We find that the solid state and EIS data agree very well, leading to the extraction of consistent D it energy distributions. Measurements carried out on pyramid-nanostructured p-Si obtained by KOH etching followed by deposition of a 10 nm ALD-Al2O3 demonstrate the application of EIS to trap characterization of a nanostructured dielectric/semiconductor interface. These results show the promise of this methodology to measure interface state densities for a broad range of semiconductor nanostructures such as nanowires, nanofins, and porous structures.