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Sensors (Basel). 2011;11(10):9160-81. doi: 10.3390/s111009160. Epub 2011 Sep 27.

Efficient phase unwrapping architecture for digital holographic microscopy.

Author information

  • 1Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, 117, Taiwan. whwang@csie.ntnu.edu.tw

Abstract

This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize throughput of the computation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC) for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system.

KEYWORDS:

FPGA; digital holographic microscopy; phase unwrapping; reconfigurable computing; system on programmable chip

PMID:
22163688
[PubMed - indexed for MEDLINE]
PMCID:
PMC3231254
Free PMC Article
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