Schematic illustration of the fabrication process of the top-gated graphene transistor with a GaN nanowire as the self-aligned top-gate. (a), A GaN nanowire is aligned on top of graphene. (b), The external source, drain and top-gate electrodes are fabricated using electron-beam lithography. (c), Deposition of 10 nm Pt metal film to form the source and drain electrodes self-aligned with the nanowire gate. (d), The schematic illustration of the cross section of the device. (e), The SEM image of the cross-section of GaN nanowire/graphene, illustrating well separated source and drain electrodes due to the nanowire shadow effect. (f), Schematic energy band diagrams of a single GaN nanowire on graphene. EF, EC, and EV are Fermi level, conduction band and valence band, respectively.