Programming enzymes to perform OR, NOR, and AND logic operations. Logic gate architectures: (a) OR gate (DE•DI1); (b) NOR gate (DE); (c) AND gate (DE•DI2•DI1); and (d) AND gate (DE2•DI1). General conditions: DE and DE2 (2 nM), DI1 and DI2 (50 nM), D2, D5, and D6 (50 nM), D7, and D8 (10 nM), substrate (80 µM) in Tris/HCl (20 mM, pH 7.4), MgCl2 (50 mM), room temp. Logic gates were prepared by incubating the appropriate DE and DI strands for 30 min prior to input addition. Substrate was added simultaneously with input strands, except for the NOR gate which was incubated with inputs for 30 min prior to substrate addition. See SI Figures 4S–7S for full time course data and control studies.