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Proc Natl Acad Sci U S A. Apr 13, 2010; 107(15): 6711–6715.
Published online Mar 22, 2010. doi:  10.1073/pnas.0914117107
PMCID: PMC2872405
Applied Physical Sciences

High-κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors


Deposition of high-κ dielectrics onto graphene is of significant challenge due to the difficulties of nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattice. Previous efforts to deposit high-κ dielectrics on graphene often resulted in significant degradation in carrier mobility. Here we report an entirely new strategy to integrate high quality high-κ dielectrics with graphene by first synthesizing freestanding high-κ oxide nanoribbons at high temperature and then transferring them onto graphene at room temperature. We show that single crystalline Al2O3 nanoribbons can be synthesized with excellent dielectric properties. Using such nanoribbons as the gate dielectrics, we have demonstrated top-gated graphene transistors with the highest carrier mobility (up to 23,600 cm2/V·s) reported to date, and a more than 10-fold increase in transconductance compared to the back-gated devices. This method opens a new avenue to integrate high-κ dielectrics on graphene with the preservation of the pristine nature of graphene and high carrier mobility, representing an important step forward to high-performance graphene electronics.

Keywords: graphene dielectric integration, carrier mobility, dielectric nanoribbon, nanoelectronics

Graphene has attracted considerable interest as a potential electronic material due to its exceptionally high carrier mobility and tunable band gap (16). Various strategies have been explored to fabricate field-effect transistors based on graphene or graphene nanostructures (613). Most of these efforts to date employ a silicon substrate as a global back gate and silicon oxide as the gate dielectric, which have led to many interesting scientific discoveries, but will be of limited use for practical applications due to the high-gate switching voltage required and the inability to independently address individual devices on the same chip. Top-gated devices with high-κ dielectrics can significantly reduce the required switching voltage and readily allow independently addressable device arrays and functional circuits, and therefore are of significant interest (14, 15).

The gate dielectric is an essential component of a transistor, which can significantly impact the critical device parameters including transconductance, subthreshold swing and frequency response. Exploring graphene for future electronics requires effective integration of high quality gate dielectrics, in particular the high-κ dielectrics. However, it has been rather challenging to deposit oxide dielectrics onto graphene without introducing defects. The deposition of high-κ dielectrics is usually achieved using atomic layer deposition (ALD), which requires reactive surface groups (1620). Functionalization of graphene surface for ALD either introduces undesired impurities or breaks the chemical bonds in the graphene lattice, inevitably leading to a significant degradation in carrier mobilities (20). Physical vapor deposition (PVD) such as electron-beam evaporation or sputtering process has also been used to deposit dielectrics without the need of surface functionalization. Although the PVD process usually yields lower quality dielectrics and can also cause significant damages to graphene (21, 22). As a result, the mobility values observed in the top-gated devices are typically nearly one order of magnitude smaller than what can be achieved in the back-gated devices (2023). Recently, the introducing of polymer or aluminum buffer layer for high-κ deposition was demonstrated with improved the device mobility (24, 25), which is still lower than that of the best back-gated graphene devices (1, 4, 5). To eventually realize high-performance graphene-based electronics, alternative approaches must be developed to deposit high quality high-κ dielectrics without damaging the pristine graphene.

Here we describe an entirely unique strategy to integrate graphene with high quality high-κ dielectrics using free-standing dielectric nanoribbons. Nanoribbons can be synthesized at high temperature with nearly perfect crystalline structure, but manipulated and assembled at room temperature. This flexibility allows the integration of normally incompatible materials and processes and can enable unique functions in electronics or photonics (2630). In this report, the dielectric properties of aluminum oxide (Al2O3) nanoribbons are explored for graphene-based electronics. Specifically, high quality dielectric Al2O3 nanoribbons were first synthesized, and then transferred onto graphene as the gate dielectrics for top-gated graphene transistors. This integration approach preserves the pristine nature of the graphene and allows us to achieve the highest room temperature carrier mobility (up to 23,600 cm2/V·s) in top-gated graphene transistors to date.

Results and Discussion

Fig. 1 illustrates our approach to fabricate top-gated graphene transistors. Mechanically peeled graphene flakes on silicon substrate were used as the starting materials in initial studies, although the approach described here can be readily extended to graphene obtained through chemical exfoliation or chemical vapour deposition. Al2O3 nanoribbons were aligned on top of the graphene through a physical dry transfer process (Materials and Methods), followed by e-beam lithography and metallization process to define the source and drain electrodes (Fig. 1A). Oxygen plasma etch was then used to remove the exposed graphene, leaving only the graphene protected underneath the dielectric nanoribbon and the source drain electrodes (Fig. 1B). The top-gate electrode was then fabricated (Fig. 1C). A typical device consists of source, drain and top-gate electrodes (Ti/Au, 50 nm/50 nm), Al2O3 nanoribbon as the top-gate dielectric, a highly doped p-type silicon substrate (< 0.004 ohm·cm) as the back gate, and a 300 nm thermal silicon oxide layer as the back-gate dielectric.

Fig. 1.
Schematic illustration of the fabrication process to obtain top-gated graphene transistors using dielectric oxide nanoribbons as the etching mask and top-gate dielectric. (A) A dielectric nanoribbon is aligned on top of graphene using a dry-transfer process ...

Aluminum oxide, with a dielectric constant of 9.1, is an important high-κ material with excellent dielectric properties, thermal and chemical stability (30). In our studies, Al2O3 nanoribbons were used as an example to demonstrate our concept of using preformed free-standing nanoribbons as the top-gate dielectrics. Al2O3 nanoribbons were synthesized through a physical vapor transport approach at 1400 °C (Materials and Methods). Transmission electron microscope (TEM) studies show that the Al2O3 nanoribbons typically have a width of 1–3 μm, and a length on the order of 10 μm (Fig. 2A). Selected area electron diffraction (SAED) study shows the nanoribbon has a single crystalline α-Al2O3 structure, oriented along left angle bracket110right angle bracket direction in its long axis, and along left angle bracket001right angle bracket direction (c-plane) in its thickness (Fig. 2A and Inset). The high resolution TEM (HRTEM) image confirms that the nanoribbon is a single crystal with nearly perfect crystalline structure free of any obvious defects (Fig. 2B). Atomic force microscopy (AFM) studies show that the nanoribbons typically have a thickness around 15–150 nm (Fig. 2C), and nearly atomically smooth surface with root mean square roughness < 0.2 nm (Fig. 2D).

Fig. 2.
Evaluation of the Al2O3 nanoribbons as dielectric material. (A) TEM image (SAED pattern, Inset) and (B) HRTEM image of an Al2O3 nanoribbon show nearly perfect crystalline structure with α-Al2O3 structure. (C) AFM image of an Al2O3 nanoribbon with ...

To understand the intrinsic dielectric properties of the nanoribbons, we have fabricated metal-insulator-metal (MIM) devices (Fig. 2E) to characterize the current tunnelling, breakdown, and dielectric characteristics. Electrical measurements of the MIM device show that current density (J) vs. electric field (E) relation exhibits typical Fowler–Nordheim (F–N) tunneling behavior with a breakdown field of 8.5 MV/cm (Fig. 2F and Inset), comparable to the best quality ALD Al2O3 film (31). This type of field-assisted tunnelling can be described by charge carrier tunnelling through a triangular barrier with

equation image


equation image


equation image

J is current density, Eox is the oxide electric field, and m* is the effective mass of the charge carrier, which is about 0.23 me, and ΦB is the barrier height (31). Fitting the J - E characteristics with the F–N tunnelling model gives a tunnel barrier of about 2.0 eV between Al2O3 and Ti, comparable to previous reports of the barrier height between ALD Al2O3 and metals of similar work function (31, 32). The relative dielectric constant is also determined from capacitance-voltage measurement as 8.5, which is larger than typical values observed in ALD Al2O3 films (31). These studies clearly demonstrate that the Al2O3 nanoribbons have dielectric properties comparable to or better than the best quality ALD Al2O3 film (31), and can function as an excellent dielectric material for top-gated graphene transistors.

The Al2O3 nanoribbons can be aligned onto the top of the graphene through a physical transfer process (Materials and Methods). Previous studies have shown that the deposition of oxide on top of graphene often introduces significant defects into the graphene structure with an obvious defect band (D-band) emerging around 1350 cm-1 in Raman spectra. To this end, we have employed micro-Raman spectroscopy to investigate the interaction between an Al2O3 nanoribbon and the underlying graphene (Fig. 3A and Inset). Micro-Raman spectra were collected from bare graphene (Point a) and Al2O3 nanoribbon covered graphene (Point b). Significantly, there is no clear difference between two Raman spectra and there is no obvious D-band (Fig. 3A), in contrast to previous studies where an obvious D-band is observed (33).

Fig. 3.
Characterization of the graphene/Al2O3 nanoribbon interface. (A) Raman spectra of the graphene with (Point b) and without (Point a) Al2O3 nanoribbon covering. The inset shows the optical image of an Al2O3 nanoribbon on graphene, the scale bar is 2 μm. ...

The excellent dielectric properties observed in the single crystalline α-Al2O3 nanoribbons readily allows us to employ them as the gate dielectrics for top-gated graphene transistors (Fig. 3B and Inset). Cross-section TEM was used to study the graphene–dielectric interface (Fig. 3 B and C). The gate stack (SiO2/graphene/Al2O3/Ti/Au) could be observed in Fig. 3B. The HRTEM image of the device shows that the graphene layers are intimately integrated with the crystalline Al2O3 nanoribbon without any obvious gap or impurities between them (Fig. 3C). Together, these studies clearly demonstrate that the physical assembly approach can effectively integrate Al2O3 nanoribbon with graphene without introducing any appreciable defects into the graphene lattice, and thus can effectively preserve the high carrier mobility in the resulting devices.

The electrical transport studies of the top-gated graphene transistors were carried out at room temperature. Fig. 4A shows the drain-source current (Ids) versus drain-source voltage (Vds) output characteristics of the transistor at various top-gate voltage (VTG) of -1.5, -1.0, -0.5, 0.0, and 0.5 V. The device delivers an on current of 675 μA at Vds = 1 V and Vg = -1.5 V. To evaluate the top-gated devices versus standard back-gated devices, we have measured the transfer characteristics, Ids versus top-gated voltage (VTG) and back-gated voltage (VBG) (Fig. 4B and Inset). Significantly, the required gate voltage swing to achieve similar current modulation in top-gate configuration is > 1 order of magnitude smaller than that in back-gate configuration. The transconductance An external file that holds a picture, illustration, etc.
Object name is pnas.0914117107eq1.jpg can be extracted from the Ids-VTG curve (Fig. 4C). At Vds = 1 V, the top-gated device exhibits a max gm of about 290 μS, which is about 15 times larger than that of the back-gated configuration (gm ~ 19.5 μS).

Fig. 4.
Room temperature electrical properties of the top-gated graphene device using Al2O3 nanoribbon as the gate dielectric. (A) Ids-Vds output characteristics, the channel width and length of the device is 2.1 μm and 4.1 μm. ...

Fig. 4D further shows two-dimensional plot of the device conductance as a function of varying VBG and VTG bias, from which we can determine the top-gate Dirac point (VTG_Dirac) shift as a function of VBG (Fig. 4E). It gives the ratio between top-gate and back-gate capacitances, CTG/CBG ≈ 14.3. This gate capacitance ratio is consistent with the improvement factor (approximately 15) in transconductance of top- versus back-gated configurations. Using the back-gate capacitance value of CBG = 11.5 nF/cm2, the top-gate capacitance is estimated to be CTG = 164.5 nF/cm2, corresponding to a relative dielectric constant of 8.4 for Al2O3 nanoribbon, which is also consistent with the value obtained from MIM devices.

To further gauge the transistor performance, it is important to determine the carrier mobility. To accurately derive the mobility value, it is necessary to exclude the contact resistance that is comparable to the graphene transistor channel resistance. The total resistance of the device can be expressed as the following (25):

equation image

Where Rchannel is the resistance of the graphene channel covered by top-gate electrode, the contact resistance Rcontact consists of the uncovered graphene section resistance and the metal/graphene contact resistance, L is the channel length, W is the channel width, and n is the carrier concentration in the graphene channel region, and can be approximated by the following equation

equation image

where n0 is the residual carrier concentration, representing the density of carriers at Dirac point (34); nTG = CTG(VTG - VTG_Dirac)/e is the carrier concentration induced by the top-gate bias away from the Dirac point, CTG can be approximated by the oxide capacitance of 164.5 nF cm-2 (the quantum capacitance is neglected here as it is > 1 order of magnitude larger approximately 2000 nF cm-2).

By fitting this model to the measured data in Fig. 4B, we can extract the relevant parameters, n0, Rcontact and μ. Fig. 4F shows the measured Rtot versus VTG (Black Line), along with the fitted curve derived from Eq. 4 (Red Line). The fitted curve agrees well with the experimental data, with a single value of the residual concentration n0 = 4.1 × 1011 cm-2, Rcontact = 1240 Ω, and the mobility μ = 22,400 cm2/V·s, which represents the highest carrier mobility value observed in top-gated graphene devices to date. The fitted contact resistance Rcontact =  ~ 1240 Ω is comparable to the Rcontact determined by four-probe measurements of similar devices (Fig. S1). The mobility value derived from top-gated configuration is also consistent with that obtained from back-gated measurement (25,600 cm2/V·s). We have studied multiple devices fabricated with the same approach, all of which exhibited carrier mobilities well exceeding 10,000 cm2/V·s (Table 1), comparable to the best reported values in back-gated devices and about one order of magnitude better than typical values previously reported for top-gated devices (17, 20, 21). The variation in mobility values is commonly seen in graphene-based devices (35), which may be attributed to variable local environment with different local potential, defects, impurities, or stress. Together, these studies clearly demonstrate that the presence of Al2O3 nanoribbon on top of graphene does not lead to any mobility degradation, in contrast to previous efforts in using ALD or PVD to deposit dielectrics on graphene.

Table 1.
The mobility values observed in multiple top-gate graphene transistors with variable Al2O3 thickness.


In conclusion, a unique strategy has been demonstrated to integrate pristine graphene with high quality high-κ dielectrics by physically assembling free-standing oxide nanoribbons. Using the Al2O3 nanoribbons as the gate dielectrics, the top-gated graphene transistors have been fabricated to exhibit superior performance with the highest carrier mobility observed in top-gated device to date. This method opens a unique avenue to integrate high-κ dielectrics on graphene with the preservation of high carrier mobility. With further optimization of nanoribbon growth and assembly process to precisely control their physical dimension and spatial location (3640), large arrays of top-gated graphene transistors or circuits can be envisioned. This physical assembly and integration approach can thus open a unique avenue to high-performance graphene electronics to impact broadly from high frequency high speed circuits to flexible electronics.

Materials and Methods

Synthesis of Al2O3 Nanoribbons.

Aluminum oxide (Al2O3) nanoribbons were synthesized through a physical vapor transport approach at 1400 °C. To grow Al2O3 nanoribbons, aluminum, and nanometer-sized Al2O3 powders with a molar ratio of 4[ratio]1 were used as the starting materials. The ceramic boat with the mixture was placed at the center of a horizontal tube furnace and an alumina piece was placed at the downstream as the deposition substrate. The temperature was raised to target temperature with a flow of 400 sccm Ar as the carrying gas. The temperature was maintained for 1 h and then naturally cooled to the room temperature.

Dry Transfer of Al2O3 Nanoribbons.

The overall process involves physical transfer of Al2O3 nanoribbons directly from a Al2O3 nanoribbon growth substrate to a graphene substrate via contact printing. Specifically, a graphene device substrate is first firmly attached to a benchtop, and the Al2O3 nanoribbon growth substrate is placed upside down on top of the graphene substrate so that the Al2O3 nanoribbons are in contact with the graphene. A gentle manual pressure is then applied from the top followed by slightly sliding the growth substrate. The Al2O3 nanoribbons are aligned by sheer forces during the sliding process. The sliding process results in direct dry transfer of nanoribbons from the growth substrate to the desired graphene substrate. The sample is then rinsed with isopropanol followed by nitrogen blow-dry, in which the capillary drying process near the Al2O3 nanoribbons can help the Al2O3 nanoribbons to be firmly attached to the substrate surface.

Characterization of Al2O3 Nanoribbons, Device Fabrication, and Measurements.

The microstructures and morphologies of the Al2O3 nanoribbons were characterized by a JEOL 6700 SEM. The lattice image of the Al2O3 nanoribbons was observed by an FEI Titan HRTEM. The thickness was measured using atomic force microscope (AFM, Veeco Dimension 5000). Oxygen plasma (Diener Electronic) was used to selectively etch away the unprotected graphene region and leave graphene ribbons underneath the Al2O3 nanoribbon mask protection. The etch time is about 160 s at a power level of 40 W. The electrical transport properties were measured by a Lakeshore probe station with home built data acquisition system

Supplementary Material

Supporting Information:


We acknowledge the Electron Imaging Center for Nanomachines at the University of California Los Angeles for the technical support of TEM, Nanoelectronics Research Facility at the University of California Los Angeles for technical support of device fabrication. This work was supported by the Henry Samueli School of Engineering and an Applied Science Fellowship (Y.H.), and by the National Institutes of Health Director’s New Innovator Award Program, part of the National Institutes of Health Roadmap for Medical Research Grant 1DP2OD004342-01 (X.D.).


The authors declare no conflict of interest.

*This Direct Submission article had a prearranged editor.

This article contains supporting information online at www.pnas.org/cgi/content/full/0914117107/DCSupplemental.


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