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Proc Natl Acad Sci U S A. Aug 12, 2008; 105(32): 11066–11070.
Published online Aug 6, 2008. doi:  10.1073/pnas.0801994105
PMCID: PMC2516247
Engineering

Large-scale, heterogeneous integration of nanowire arrays for image sensor circuitry

Abstract

We report large-scale integration of nanowires for heterogeneous, multifunctional circuitry that utilizes both the sensory and electronic functionalities of single crystalline nanomaterials. Highly ordered and parallel arrays of optically active CdSe nanowires and high-mobility Ge/Si nanowires are deterministically positioned on substrates, and configured as photodiodes and transistors, respectively. The nanowire sensors and electronic devices are then interfaced to enable an all-nanowire circuitry with on-chip integration, capable of detecting and amplifying an optical signal with high sensitivity and precision. Notably, the process is highly reproducible and scalable with a yield of ≈80% functional circuits, therefore, enabling the fabrication of large arrays (i.e., 13 × 20) of nanowire photosensor circuitry with image-sensing functionality. The ability to interface nanowire sensors with integrated electronics on large scales and with high uniformity presents an important advance toward the integration of nanomaterials for sensor applications.

Keywords: nanomaterials, printable electronics, devices, transistors, imager

Chemically derived, synthetic nanomaterials with low dimensionality and well defined atomic composition present a unique route toward miniaturization of electronic and sensor components while enhancing their performance and functionality (15). To date, a broad spectrum of single crystalline nanomaterials with tailored properties have been synthesized, and have been successfully demonstrated as the building blocks of various high-performance device elements, such as transistors (617), optical devices (1820), sensors (2126), energy-scavenging devices (27), and simple circuit structures (7, 17, 19, 28). These synthetic materials present a number of key advantages over their bulk counterparts. For instance, downscaling of the active sensing material to the nanoscale regime has been shown to enhance the sensitivity of chemical, biological, and optical sensors by orders of magnitude (2126). To enable the implementation of nanosensors for various technological applications, on-chip integration with electronics is needed to enable automated and accurate processing of the signal. Here, we demonstrate an all-integrated, heterogeneous nanowire (NW) circuitry, capable of detecting and amplifying an optical signal with high sensitivity and responsivity. By implementing our recently developed contact printing technology (29, 30), large arrays of optically active CdSe NWs and high-mobility core/shell Ge/Si NWs are assembled at well defined locations on substrates, and configured as integrated sensor and electronic active components of an all-nanowire circuitry with image-sensing capability.

Results and Discussion

In this work, direct band gap CdSe NWs were used as a model system for the optical sensor elements, capable of detecting visible light with high sensitivity. CdSe- and CdS-based nanomaterials such as quantum dots and NWs have been extensively explored in the past, and their superb optical and opto-electrical properties have been reported in detail by various groups (3133). Notably, NWs (for instance, in the case of ZnO NWs) have been shown to be ideal materials for photodetection with significantly higher sensitivities than their bulk counterparts, arising from their high surface area-to-volume ratio that results in high density of surface states (21, 33). The surface states trap the photogenerated holes and, therefore, effectively increase the electron carrier lifetime that results in the enhancement of the photocurrent (21). To implement CdSe NWs as optical sensors, Schottky devices were fabricated by contacting the NWs with high work function Ni/Pd (5/45 nm) source (S) and drain (D) electrodes (Fig. 1A). NWs were grown intrinsically without any intentional doping by using the previously reported vapor–liquid–solid process (see Methods; 34), and as expected they exhibited n-type behavior (Fig. 1B) because of their surface Fermi level pinning. From photoluminescence measurements, a band gap of ≈1.76 eV was extracted (see supporting information (SI) Fig. S1), which is consistent with the reported bulk value, and is indicative of stoichiometric composition. The electrical characteristic of a representative CdSe NW Schottky device is shown in Fig. 1B. The device exhibits large dark resistance Rdark ≈140 GΩ because of the Schottky barriers at the S/D interfaces that severely limit the carrier injection from the metal into the chemically intrinsic semiconductor NWs. On white light illumination (halogen light source, 4.4 mW/cm2), a drastic decrease of ≈100 times in the device resistance (Rlight ≈2 GΩ) is observed that is attributed to the efficient electron/hole photogeneration and field-induced carrier separation in CdSe NWs (Fig. 1A). The photocurrent gain in our NW devices is comparable to the best reported values in literature for physical vapor-deposited CdSe thin films. However, for such thin-film devices, the exact gain (ranging from 10 to 1,000 times for ≈80 mW/cm2 illumination) is shown to highly depend on the annealing and deposition temperature conditions that effectively control the film stoichiometry, morphology, and crystallinity (35). In distinct contrast, NWs are single crystalline with controlled composition, and require only ambient temperature processing for their deposition (i.e., assembly) on substrates, making them highly compatible with a wide range of substrates, including plastics and papers.

Fig. 1.
Highly sensitive, direct band-gap NW photodiodes. (A) SEM (Top), schematic (Middle), and the band diagram (Bottom) of a CdSe NW photodetector with Ni/Pd Schottky S/D contacts. (B) IDS-VGS and IDS-VDS (Inset) curves of a representative CdSe NW device before ...

To further characterize the CdSe NW photosensors, transient and illumination intensity-dependent measurements were performed. Time-resolved photoresponse measurements were conducted for multiple illumination cycles as depicted in Fig. 1C. Each photoresponse cycle consists of three transient regimes—a sharp rise (τ ≈0.7 sec), steady state, and sharp decay (τ ≈0.7 sec). We note that our time constants are larger than the best reported values for nanowires in the literature (21, 33). We attribute this to (i) the quality of our nanowires, which can be readily improved in the future through growth optimization, and (ii) the measurement setup. However, this response time is adequate for the purpose of this work, and in principle it can be drastically improved in the future, if desired. Importantly, a nearly identical response is observed for multiple cycles which demonstrates the robustness and reproducibility of the NW optical sensors. The illumination power dependence of the photoresponse is shown in Fig. 1D, exhibiting two distinct regimes with the transition intensity of ≈2mW/cm2. This nonlinear photoresponse has also been reported in other NW photodetectors, and has been attributed to the charge-trapping and recombination processes due to the dominant surface states in the forbidden gap of NWs (35, 36).

Although the miniaturized nanosensor elements, such as the CdSe NW photodetectors shown here, provide high sensitivity to the environment with high spatial resolution, they are inherently limited to low signal amplitude (i.e., current), and therefore require an eventual signal amplification via electronic circuitry to enable effective data processing. To date, this important requirement has not yet been addressed. Here, we report direct, on-chip amplification of the nanosensor signal by using an all-NW circuitry without any external wiring. The schematic, SEM, and optical images of a fabricated all-nanowire circuit is shown in Fig. 2, consisting of three active device elements: (i) optical nanosensors (NSs) based on either a single or parallel arrays of multiple CdSe NWs, (ii) a high-resistance field-effect transistor (FET) (T1) based on parallel arrays of 1–5 Ge/Si core/shell NWs, and (iii) a low-resistance buffer FET (T2) with the channel consisting of parallel arrays of ≈2,000 NWs. The all-nanowire circuitry utilizes T1 to match the output impedance of the NS in a voltage divider configuration. Once the illumination-dependent NS current is translated into potential VG2, the output current of T2 is modulated according to its transfer characteristics, resulting in ≈5 orders of magnitude amplification of the NS current signal.

Fig. 2.
Heterogeneous NW assembly for an all integrated, sensor circuitry. (A) Circuit diagram for the all-nanowire photodetector, with high-mobility Ge/Si NW FETs (T1 and T2) amplifying the photoresponse of a CdSe nanosensor. (B) Schematic of the all-nanowire ...

To enable the successful fabrication of the all-integrated, heterogeneous NW circuitry, it is essential to assemble highly regular NW arrays with high uniformity at well defined locations on the substrate. Recently, we have developed a contact printing technology for direct transfer of highly ordered and aligned NW arrays on various receiver substrates with high reproducibility over large areas (29, 30). In this approach, a dense “lawn” of single crystalline NWs with controlled composition is first grown on a growth substrate by using the vapor–liquid–solid process, followed by the transfer of NWs to a receiver substrate by a directional sliding. Before the printing process, the receiver substrate is coated with a photolithographically patterned resist layer that enables for patterned NW assembly on resist removal in acetone. We incorporated this assembly approach for enabling the fabrication of the all-nanowire sensor circuitry. First, highly aligned CdSe and Ge/Si NW arrays were assembled at predefined locations on a Si/SiO2 (50 nm, thermally grown) substrate by using a two-step printing process (see Methods). Ni/Pd S/D electrodes were then patterned on NW arrays followed by atomic layer deposition (ALD) of 8- to 9-nm-thick HfO2 film as the high-κ gate dielectric. Finally, the HfO2 layer was selectively etched in hydrofluoric acid at the bonding pads and vias, and the top gate electrodes (Ni/Pd) were patterned on Ge/Si NWs while simultaneously forming the vias between the two metal layers (see Methods). Fig. 2C shows an optical microscopy image of a fabricated circuit and scanning electron microscopy (SEM) images of each individual component, clearly demonstrating the highly ordered NW positioning and the on-chip integration. The achieved NW alignment is highly desirable for high-performance and highly uniform transistor and sensor arrays. For transistors, a high degree of alignment, without NW crossing, is needed to reduce variation in gate electrostatics coupling and NW channel length, both of which directly affect the switching performance. Similarly, for CdSe optical sensors, the alignment is critical for uniform response of the devices, but also more uniquely to enable well defined polarized sensitivity that arises from the 1D nature of NWs (18). The polarization-dependent photoconduction measurements of single and parallel arrays of CdSe NWs are depicted in Fig. S2. In particular, near-identical polarization-dependent response is observed for various printed CdSe NWs with similar minima and maxima polarization angles, which further illustrates the highly aligned assembly of NWs by contact printing. This is in distinct contrast to the randomly aligned NWs assembled by the drop-casting method that show different polarized response depending on the orientation of the particular wire.

The all-nanowire photosensor circuits were measured at both the single-device component and circuit levels to characterize their operational performance. Fig. 3A shows the transfer characteristics of T1 and T2, both exhibiting clear p-type switching characteristics with ION ≈4 μA and 1 mA, respectively. Further detailed characterization of representative Ge/Si NWs FETs is presented in Fig. S3. In summary, the Ge/Si NW FETs showed minimal hysteresis (<200 mV) owing to the passivation from the environment (i.e., humidity) by the top gate stacks, and the high-quality gate dielectrics deposited by ALD (38). A hole mobility range of μp = 30–120 cm2/V·s is extracted from the standard square law model (Fig. S3D). Although the highest μp of our NWs is comparable to that of Si p-metal oxide semiconductor FETs, the mobility is ≈7 times lower than the best reported value for Ge/Si NW FETs (9, 37). We attribute this to the nonideal high-κ/NW interfaces and/or non-ohmic metal contacts in our fabricated device structures.

Fig. 3.
All-integrated NW sensor circuitry. (A) Transfer characteristics of parallel array Ge/Si NW FETs with channel width of ≈1 μm (dashed line, T1) and ≈300 μm (solid line, T2) with VDS = 3V. The blue box represents the active ...

Ge/Si NW FETs were found nonresponsive to white light illumination which guaranteed no undesired interference (see Fig. S4). For the circuit level operation, the operating bias, VDD was maintained at −3V for all measurements. The gate electrode for T1 was biased at VG1 = 3V (corresponding to RT1 = 1–2 GΩ) to match the output impedance of the CdSe NS. The output signal of a circuit for multiple white light illumination cycles (4.4 mW/cm2) is depicted in Fig. 3B, showing average dark and light currents of ≈80 μA and ≈300 μA, respectively. Importantly, this output current is quantitatively consistent with the value that is estimated based on the circuit layout and the electrical properties of the single-device components. The output current of the circuit can be estimated from the transfer characteristics of T2 and the output voltage of the voltage divider, which is also the input to T2. The output of the voltage divider, VG2 can be estimated as VG2 = VDD × RT1/(RT1 + RNS), corresponding to VG2 ≈ −0.02V and −1.11V for dark and light (RNS-dark ≈140 GΩ and RNS-light ≈2 GΩ; Fig. 1B) scenarios, respectively, which is in good agreement with the measurements (blue curve, Fig. 3B). The VG2 swing defines the operation regime of T2 as depicted in the transfer characteristics (Fig. 3A). This operation regime corresponds to an output current swing of 87–310 μA, consistent with the measured values and the PSpice modeling (see Fig. S5).

The intensity-dependent photoresponse measurements were conducted as shown in Fig. 3C to further characterize the integrated circuits. The trend is nearly identical to the photoresponse of the single CdSe NW device (Fig. 1D), suggesting that the signal amplification by the circuit is nearly linear for the illumination intensity of 0–13 mW/cm2. The circuit level measurements demonstrate the successful operation of NW circuits for effective amplification of the small photocurrent generated by the NS elements.

To further demonstrate the versatility of our approach, we fabricated large arrays (i.e., 13 × 20) of the all-nanowire circuits on a chip (Fig. 4A), and measured the photoresponse of each individual circuit element. Rather than single CdSe NWs, parallel arrays of 5–10 NWs were used as the active element of each NS to enhance the yield and reduce the variation by taking advantage of the averaging effect (see Fig. S6). It was found that ≈80% of the circuits demonstrated successful photoresponse operation as depicted in the failure analysis map (Fig. 4B). The functional circuits exhibited a mean photocurrent of ≈420 μA with a standard deviation of ±165 μA. The reasonably small circuit-to-circuit variation arises from the uniformity of the assembled nanowire arrays. The three major causes for circuit failure were (i) fabrication defects (i.e., poor metal lift-off and gate dielectric breakdown), (ii) failed CdSe printing, and (iii) weak photoresponse from CdSe NWs (i.e., defective NWs), which represent ≈10%, 5%, and 5% of the fabricated circuits accordingly. The high yield of the operational circuits with a high level of complexity proves the potential of the NW technology and our parallel array assembly approach for large-scale sensor and electronic integration. In the future, this yield can be further enhanced through NW synthesis and fabrication-processing optimization.

Fig. 4.
Large-scale and heterogeneous integration of NWs for image sensing. (A) Optical image of an array of all-nanowire photodetector circuitry with each circuit element serving as an independently addressable pixel. (B) A defect analysis map showing the functional ...

The large NW circuit matrix can readily function as an image sensor. To demonstrate this feasibility, as a proof of concept, a halogen light source was focused and projected onto the center of the matrix. The output current was measured for each individual working circuit and digitized into a 0–100 scale with “0” and “100” representing the maximum and minimum measured intensity, respectively (see SI Text). Each of the circuits was regarded as a pixel and the measured intensity levels of the circuits were incorporated into a 2D plot to generate a contrast map shown in Fig. 4D. The contrast map clearly demonstrates the spatial intensity variation from the center to the outer edge of the circuit matrix, precisely matching the intensity profile of the projected light source, thus showing a preliminary imaging function with an all-nanowire circuit array. In future, significant downscaling of the pixel size can be achieved by reducing the feature size (for instance, channel length and width) of the Ge/Si NW FETs and the metal interconnects.

In summary, the large-scale assembly of NWs for heterogeneous, sensor circuitry with on-chip integration was demonstrated. The sensory and electronic functionalities of NWs have been interfaced through heterogeneous integration of direct band gap CdSe NWs and high-mobility Ge/Si NWs. Active elements consisting of both single and parallel arrays of NWs were incorporated to enable the circuit operation, involving 5 orders of magnitude current amplification of the nanosensor's signal. Importantly, by using parallel arrays of NWs as the active component of each device, the reliability and uniformity was significantly enhanced, therefore, enabling a reliable large-scale integration path for the demonstration of an image sensor. In the future, the process can be expanded to other optically active NWs, which combined with the scaling of the fabricated devices may enable high-resolution and multicolor imaging. This work not only demonstrates the nanowire device integration at an unprecedented scale, but also illustrates and presents a system based on printed NW arrays that may enable a number of technological applications by using NWs as the building blocks.

Methods

Nanowire Growth.

Ge/Si core/shell NW growth process can be found in ref. 9. CdSe nanowires were grown in a custom-made CVD system with a single zone, resistive heating furnace (Lindburg Blue), which accommodates one-inch diameter quartz tubes. Gold nanoparticles with 30-nm diameter were deposited on Si/SiO2 substrates and served as catalysts for the vapor–liquid–solid growth process. Before the growth, 1.5 g of CdSe powder (Alfa Aesar, 99.999%) was placed in a quartz boat and loaded into the center of the heating zone in the furnace. Then, the growth substrate was placed at the downstream, ≈9.5 cm away from the center of the furnace. The nanowire growth was carried out with the furnace temperature (precursor temperature) at 700°C and 50 standard cubic centimeters per minute continuous flow of hydrogen. The system pressure was stabilized at 30 torr with a pressure controller and the growth was carried out for 1.5 h.

Nanowire Contact Printing.

An alignment mark layer was first created on a Si/SiO2 substrate. Then a layer of photoresist (Shipley 1805 diluted in propylene glycol monomethyl ether acetate with 1:3 volume ratio) was spin-coated on the substrate, and lithographically patterned to define printing channels for the CdSe nanowire assembly. The details of the printing process can be found in ref. 29. After CdSe nanowire printing, the photoresist was removed in acetone followed by a second printing step for Ge/Si nanowires by using an identical process flow.

Device Fabrication.

After contact printing of CdSe and Ge/Si nanowires, source-drain contact electrodes were patterned with photolithography. Then Ni (5 nm)/Pd (45 nm) was evaporated with an electron beam evaporator followed by lift-off. HfO2 high-κ gate dielectric film was then deposited by using an atomic layer deposition tool. In this process, tetrakis(dimethylamino) hafnium maintained at 110°C and water were used as the precursors. HfO2 was deposited for 85 cycles (≈9 nm thick) at 140°C, with each cycle consisting of a 1-sec tetrakis(dimethylamino) hafnium precursor pulse, 20-sec nitrogen purge, 1-sec water vapor pulse, and 40-sec nitrogen purge. Thereafter, etching windows on source-drain bonding pads and the bridges (vias) between the Ge/Si transistors were photolithographically patterned, and the HfO2 was chemically etched with 5% HF for 35 sec. Finally, Ni (5 nm)/Pd (45 nm) for the top metal gate electrodes of T1 and T2, and the vias were fabricated by photolithography, metallization, and lift-off.

Supplementary Material

Supporting Information:

Acknowledgments.

We thank A. M. Peczalski for insightful discussions, and Professor M. Wu and Dr. K. Yu for help with optical measurements. All fabrication was performed in the Berkeley Microfabrication Laboratory. This work was supported by Defense Advanced Research Projects Agency/Microsystems Technology Office, Intel, and Materials Structures and Device Focus Center. The nanowire synthesis was supported by a Laboratory Directed Research and Development Project from Lawrence Berkeley National Laboratory. J.C.H received a graduate fellowship from Intel Foundation.

Footnotes

The authors declare no conflict of interest.

This article is a PNAS Direct Submission.

This article contains supporting information online at www.pnas.org/cgi/content/full/0801994105/DCSupplemental.

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