Results: 4

Figure 2

Figure 2. Images illustrating steps of nanomesh fabrication process. From: Graphene nanomesh.

a, An AFM phase contrast image of the annealed block copolymer film on graphene shows hexagonal packed PMMA domains in the PS matrix. b, An SEM image of a porous PS film obtained by selectively removing the PMMA domains. c, An SEM image of the SiOx nanomesh mask after reactive ion etching with PS mask. d, An SEM image of a GNM structure after removing top SiOx mesh mask. All scale bars indicate 100 nm.

Jingwei Bai, et al. Nat Nanotechnol. ;5(3):190-194.
Figure 3

Figure 3. TEM studies of graphene and thin layer graphite nanomesh. From: Graphene nanomesh.

a,e, TEM images of GNMs with periodicity of 39 nm and neck width of 14.6 nm obtained with block copolymer P(S-b-MMA) of molecular weight of 77000 g mol−1. b,f, GNM with periodicity of 39 nm and neck width of 11.2 nm obtained with controlled over etching. c,g, GNM with periodicity of 39 nm and neck width of 7.1 nm obtained with additional over etching. d,h, GNM with periodicity of 27 nm and neck width of 9.3 nm obtained with block copolymer P(S-b-MMA) of smaller molecular weight of 47700 g mol−1. The dark strips in the background of the images originate from the lacey carbon on TEM grids. Scale bars for (a-d) indicate 200 nm and scale bars for (e-h) indicate 100 nm. i-l, Histograms of the GNM neck width for (e-h) with average neck widths of 14.6 nm, 11.2 nm, 7.1 nm and 9.3 nm; and standard deviations of 2.0 nm, 1.9 nm, 1.5 nm and 1.3 nm, respectively.

Jingwei Bai, et al. Nat Nanotechnol. ;5(3):190-194.
Figure 1

Figure 1. Schematic of making graphene nanomesh. From: Graphene nanomesh.

a, A pristine graphene flake on top of silicon oxide substrate as starting material. b, The graphene flake is covered by a thin layer of evaporated SiOx and a thin film of spin coated block copolymer poly(styrene-block-methyl methacrylate) (P(S-b-MMA)). The SiOx here is used as protecting layer and the grafting substrate for the following block copolymer nanopatterning. c, The P(S-b-MMA) block copolymer film is annealed and developed, leaving the porous PS matrix as nanomesh template for further patterning. d, Fluoride based reactive ion etching (RIE) to penetrate oxide layer and partially degrade PS film, and form SiOx nanomesh hard mask. e, Graphene in the exposed area is etched away by O2 plasma. f, After HF dip to remove oxide mask, a GNM is obtained. g, Free standing GNM can be lifted off from the substrate by etching away underlying silicon oxide.

Jingwei Bai, et al. Nat Nanotechnol. ;5(3):190-194.
Figure 4

Figure 4. Room temperature electrical properties of graphene nanomesh device. From: Graphene nanomesh.

a, A schematic of a GNM-FET. The device is fabricated on heavily doped silicon substrate with 300-nm SiO2 as the gate dielectric. The electronic measurement was done in ambient at room temperature without removing top oxide layer. b, An SEM image of a GNM device made from nanomesh with a periodicity ca. 39 nm, and neck width of ca. 10 nm. Scale bar indicates 500 nm. c, Drain current (Id) versus drain-source voltage (Vd) recorded at different gate voltage for a GNM device with channel width of ~ 2 μm and channel length of ~ 1 μm. The on state conductance at Vg=−10 V is comparable to an array of 100 parallel GNR devices. d, Transfer characteristics for the device in (c) at Vd = −10 mV, −100 mV and −500 mV. The ratio between Ion to Ioff for this device is ~ 14 at Vd = −100 mV. e, Transfer characteristics at Vd = −100 mV for GNMs with different estimated neck widths of ~15 nm (device channel width 6.5 μm and length 3.6 μm), ~10 nm (channel width 2 μm and length 1 μm), and ~7 nm (channel width 3 μm and length 2.3 μm).

Jingwei Bai, et al. Nat Nanotechnol. ;5(3):190-194.

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